The present invention relates to techniques for controlling signal offsets, and more particularly, to techniques for dynamically correcting offsets associated with integrated circuit buffers and amplifiers using programmable resources.
Generally, interface circuitry such as input and output buffer circuits are used to amplify and/or condition signals for detection or transmission. In the case of an input buffer in a telecommunication system, the circuit receives an input signal that has typically undergone degradation and attenuation as it propagated through a transmission link. The function of the input buffer is therefore to amplify and recondition the received signal, and in some cases to provide frequency equalization, so that the receiver circuitry can properly resolve the incoming bits. In the case of an output buffer, the circuit is typically required to drive an output signal at the appropriate levels for a given transmission link. In either case, any signal offset that may be caused by the buffer circuitry can contribute to operational error. For example, any offset in the first stage of a typical multi-stage limiting amplifier in the analog front-end of a receiver is amplified by subsequent stages. The amplified offset reduces the available timing margins needed to resolve incoming data bits. This causes an increase in the bit error rate (BER) of the receiver circuit. The amount of overall voltage offset grows proportionally to square root of sum of squares of individual stage offsets, where summation is done for all stages, hence the number of cascaded buffer circuits in the signal path and the greater the amount of offset, the greater the potential increase in BER. This is further exacerbated as integrated circuits shrink in size and operate at reduced voltage margins. In the case of output buffers, offsets cause undesirable duty cycle distortion for the output signal. Various offset cancellation techniques have therefore been developed to eliminate or reduce the adverse effects of offset signals.
Generally, offset cancellation schemes either provide for a one-time correction of signal offset usually upon power-up or initial configuration, or use an internal feedback loop to continuously monitor and correct for offset. Conventional one-time offset calibration techniques require addition circuitry to enable/disable offset cancellation and are only accurate at the time the device is calibrated. Furthermore, circuits using one-time offset calibration are typically affected by environmental variations such as changes in temperature after calibration which reduces their efficacy. Conventional dynamic offset cancellation circuits with an internal feedback loop typically assume that input signals are DC-balanced, and require additional front-end circuitry specific to a particular analog or digital system to complete the feedback loop. They therefore tend to require more complex circuitry which also adds to loading conditions.
There is therefore a need for circuits and methods to reduce or eliminate signal offsets in order to improve integrated circuit operational performance.